1. Field of the Invention
The present invention relates to integrated circuit packaging. More particularly, the present invention relates to the arrangement for attaching a die-down-oriented integrated circuit in a die-up-oriented package such a chip scale package land grid array or a lead frame.
2. Description of the Prior Art
Integrated circuits are connected to other integrated circuits or other electrical devices via printed circuit boards having metal connectors. The integrated circuits are formed on sections of semiconductor wafers or die using well-known fabrication techniques. An integrated circuit of a die is attached to a substrate designed to provide structural support, thermal protection, and a means to fan out metal connectors or traces from the circuit to the printed circuit board. The combination of the integrated circuit and its substrate/metal connectors is referred to as the integrated circuit package. The package is essentially a housing that is used either to plug the device into sockets of the circuit board or to solder the device onto surface contacts of the board.
The most common type of semiconductor packaging to have been used is the small-scale outline package such as shown in FIG. 1. That package includes a semiconductor chip 10 supported on and attached to a die attach pad (DAP) 11 encapsulated in an encapsulating material 12. The chip 10 includes bond pads represented by pads 13 and 14 connected to bond wires 15 and 16 that are connected to respective lead frames 17 and 18 of a lead frame. The lead frame connects the chip 10 to traces of the printed circuit board. The bond pads of the chip 10 are located on the top surface of the chip 10. The desired connection of the chip 10 to the printed circuit board has pads 13 and 14 connected to the lead frames 17 and 18 on the same side of the package.
FIG. 2 illustrates an alternative package design. That package includes mounting of the die or chip 20 on a DAP 21. Contacts 22 and 23 of the chip 20 are coupled to a bottom side of the lead frame by way of wire bonds 24 and 25 to lead frame leads 26 and 27. The construction process for producing the package of FIG. 2 is substantially the same as the process used to produce the package of FIG. 1. The package of FIG. 2 is commonly referred to as a die-down package while that of FIG. 1 is a die-up package.
The packaging types described must be designed with common connector protocols in mind. That is, there are conventions for the ways in which electronic devices are interconnected, requiring the chip manufacturers to fabricate chips and, more specifically, their contacts, with a particular orientation. The contact pads of the packages shown in FIGS. 1-3 must be positioned to match the mounting configuration established on the printed circuit board. For example, a chip to be coupled to a high-potential power rail, a low potential power rail, two inputs and two outputs must be configured so that the chip's contacts are matched to the traces associated with each of those elements. For a die-down package such as the package shown in FIG. 2, the chip is fabricated so that its contacts are on what becomes the bottom of the structure. On the other hand, a chip packaged in a standard lead frame package such as that shown in FIG. 1, is fabricated so that its contacts are on what is the top of the structure. Thus, there are two types of chip orientations that must be fabricated as a function of the particular packaging type employed. Those chips that are “die down” and those that are “die up.” While it is common practice to fabricate both types of die orientations, it would be more cost effective to be able to fabricate just one type that could be used in either type of package configuration.
Therefore, what is needed is a packaging arrangement that would permit the connection of a die-down chip in a die-up configuration.